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CY28551-3
Universal Clock Generator for Intel, VIA and SIS(R)
Features
* * * * * * * * * * * Compliant to Intel(R) CK505 Selectable CPU clock buffer type for Intel P4 or K8 selection Selectable CPU frequencies Universal clock to support Intel, SiS and VIA platform 0.7V Differential CPU clock for Intel CPU 3.3V Differential CPU clock for AMD K8 100-MHz differential SRC clocks 96-MHz differential dot clock 133-MHz Link clock 48-MHz USB clocks 33-MHz PCI clock * * * * * * * Dynamic Frequency Control Dial-A-Frequency(R) WatchDog Timer Two Independent Overclocking PLLs Low-voltage frequency select input I2C support with readback capabilities Ideal Lexmark Spread Spectrum profile for maximum electromagnetic interference (EMI) reduction * 3.3V power supply * 56-pin QFN packages
CPU x2 SRC x6 SATA x1 PCI x6 REF x3 LINK x2 DOT96 x1 24_48M x1 48M x1
Block Diagram
Xin Xout
VDD_REF
Pin Configuration
REF[2:0]
PLL Reference
VDD_CPU
PLL1 CPU
DOC[2:1]
FS[D:A]
Divider
CPUT[1:0] CPUC[1:0] VDD_PCIEX
PCIET [6:2] PCIEC 6:2]
VDD_SATA
SEL_P4_K8
PCIET0 /SATAT PCIEC0 /SATAC
PLL2 PCIEX
Divider
M ultiplexer Controller
SEL[1:0]
VDD_DOT
DOT96T/SATAT/LINK0 DOT96C/SATAC/LINK1
PCIEXT2 PCIEXC2 VDDPCIE PCIEXT3 PCIEXC3 VSSPCIE PCIEXT4 PCIEXC4 VDDPCIE PCIEXC5 PCIEXT5 PCIEXC6/PCI_STP# PCIEXT6/CPU_STP#
PLL4 Fixed
VTTPW R_GD#/PD
Divider
VDD_48 48M
SEL24_48
24_48M
RESET_I# SDATA SCLK
I2C Logic
W DT
SRESET#
* Indicates internal pull-up ** indicates internal pull-down
Cypress Semiconductor Corporation Document #: 001-05677 Rev. *D
*
198 Champion Court
*
San Jose, CA 95134-1709
* 408-943-2600 Revised August 03, 2006
VSSPCIE
PLL3 SATA
Divider
VDD_PCI
*SEL0/ PCI5 VDD48 **SEL24_48 / 24_48M **SEL1/48M VSS48 VDDDOT LINK0/DOT96T/SATAT LINK1/DOT96C/SATAC VSSDOT VDDSATA SATAT/PCIEXT0 SATAC/PCIEXC0 VSSSATA NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14
PCI4/*SELP4_K8 VDDPCI PC3/*FSB PCI2/**FSA VSSPCI PCI1/PCIEREQ#A PCI0/PCIEREQ#B **DOC1
14.318-MHz Crystal
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 Xout 41 VDDREF 40 SCLK 39 SDATA 38 VTTPWRG#/PD 37 CPUT0 36 CPUC0 35 VDDCPU 34 CPUT1 33 CPUC1 32 VSSCPU 31 **DOC2 30 VSSA 29 VDDA
CY28551-3
PCI[6:0]
15 16 17 18 19 20 21 22 23 24 25 26 27 28
RESET_I#/SRESET# REF0/ **FSD REF1 /**FSC REF2/**MODE VSSREF Xin
CY28551-3
Pin Description
Pin No. 1 Name *SEL0/PCI5 Type Description I/O, PU 3.3V-tolerant input for output selection/33-MHz clock output. Refer to Figure 1 for selection options. Internal 150k pull-up PWR 3.3V power supply for outputs.
2 3
VDD48
**SEL24_48#/24_4 I/O, PD 3.3V-tolerant input for 24-MHz, 48-MHz selection/24_48MHz clock output. Internal 8M 150k pull-down 1 = 24 MHz, 0 = 48 MHz Intel Type-3A output buffer **SEL1/48MHz I/O, PD 3.3V-tolerant input for output selection/48-MHz clock output. Refer to Figure 1 for selection options Internal 150k pull-down GND PWR Ground for outputs 3.3V power supply for outputs
4
5 6 7
VSS48 VDDDOT
LINK0/DOT96T/SA O, Link output for VIA and SIS, Differential 96-MHz True clock and 100-MHz differential TAT SE/DiF True clock. The output was selected by SEL[0:1] LINK1/DOT96C/SA O, Link output for VIA and SIS, Differential 96-MHz Complement clock output and TAC SE/DiF 100-MHz differential Complement clock. The output was selected by SEL[0:1] VSSDOT VDDSATA PCIEXT0/SATAT PCIEXC0/SATAC/ VSSSATA VSS PCIEXT2 PCIEXC2 VDDPCIE PCIEXT3 PCIEXC3 VSSPCIE PCIEXT4 PCIEXC4 VDDPCIE PCIEXC5 PCIEXT5 PCIEXC6/PCI_ST OP# GND PWR Ground for outputs 3.3V power supply for outputs
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
O, DIF True differential SRC clock output/True differential SATA SRC clock output. Intel type SR output buffer O, DIF Complement differential SRC clock output/Complement differential SATA SRC clock output. Intel type SR output buffer GND GND Ground for outputs Ground for outputs
O, DIF True 100-MHz Differential Serial reference clock. Intel type SR output buffer O, DIF Complement 100-MHz Differential Serial reference clock. Intel type SR output buffer PWR 3.3V power supply for outputs. O, DIF True 100-MHz Differential Serial reference clock. Intel type SR output buffer O, DIF Complement 100-MHz Differential Serial reference clock. Intel type SR output buffer GND Ground for outputs. O, DIF True 100-MHz Differential Serial reference clock. Intel type SR output buffer O, DIF Complement 100-MHz Differential Serial reference clock. Intel type SR output buffer PWR 3.3V power supply for outputs. O, DIF Complement 100-MHz Differential Serial reference clock. Intel type SR output buffer O, DIF True100-MHz Differential Serial reference clock. Intel type SR output buffer I/O, DIF 3.3V-tolerant input for stopping PCI and SRC outputs/Complement 100-MHz Differential serial reference clocks. The two multifunction pins are selected by MODE. Default PCIEX6. Intel type SR output buffer
27
PCIEXT6/CPU_ST I/O, DIF 3.3V-tolerant input for stopping CPU outputs/True 100-MHz Differential serial OP# reference clocks. The two multifunction pins are selected by MODE. Default PCIEX6. Intel type SR output buffer VSSPCIE VDDA GND PWR Ground for outputs. 3.3V power supply for PLL. Page 2 of 29
28 29
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CY28551-3
Pin Description (continued)
Pin No. 30 31 VSSA **DOC2 Name Type GND I, PD Ground for PLL. Dynamic Over Clocking pin 0 = normal, 1 = Frequency will be changed depend on DOC register. Internal 150k pull-down. Ground for outputs. Description
32 33 34 35 36 37 38
VSSCPU CPUC1 CPUT1 VDDCPU CPUC0 CPUT0 VTT_PWRGD#/PD
GND
O, DIF Complement Differential CPU clock output. Intel type SR output buffer. O, DIF True Differential CPU clock output. Intel type SR output buffer. PWR 3.3V power supply for outputs. O, DIF Complement Differential CPU clock output. Intel type SR output buffer. O, DIF True Differential CPU clock output. Intel type SR output buffer. I 3.3V LVTTL input. This pin is a level-sensitive strobe used to latch the HW strapping pin inputs. After asserting VTT_PWRGD# (active LOW), this pin becomes a real-time input for asserting power-down (active HIGH) SMBus compatible SDATA SMBus compatible SCLOCK. 3.3V power supply for outputs. 14.318-MHz Crystal Output 14.318-MHz Crystal Input Ground for outputs.
39 40 41 42 43 44 45
SDATA SCLK VDDREF XOUT XIN VSSREF **MODE/REF2
I/O I PWR O I GND
I/O, SE, 3.3V-tolerant input for selecting output/14.318-MHz REF clock output. Internal 150k PD pull-down 0 = Desktop, 1 = Notebook Intel Type-5 output buffer I/O,PD, 3.3V-tolerant input for CPU frequency selection/14.318-MHz REF clock output. SE Internal 150k pull-down Intel Type-5 output buffer Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications. I/O,PD, 3.3V-tolerant input for CPU frequency selection/14.318-MHz REF clock output. SE Internal 150k pull-down Intel Type-5 output buffer Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
46
**FSC/REF1
47
**FSD/REF0
48 49
RESET_I#/SRESE I/O, OD 3.3V-tolerant input for reset all of registers to default setting. T# 3.3V LVTTL output for watchdog reset signal **DOC1 I, PD Dynamic Over Clocking pin 0 = normal, 1 = Frequency will be changed depend on DOC register. Internal 150k pull-down
50
**CLKREQ#B/PCI0 I/O,SE, 3.3V tolerant LVTTL input for Output enable of PCIEX 4,5 via register PD selection/33-MHz clock output. Internal 150k pull-down Intel Type-3A output buffer **CLKREQ#A/PCI1 I/O,SE, 3.3V-tolerant LVTTL input for Output enable of PCIEX 6,7 via register PD selection/33-MHz clock output. Internal 150K pull-down Intel Type-3A output buffer VSSPCI GND Ground for outputs.
51
52
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CY28551-3
Pin Description (continued)
Pin No. 53 Name **FSA/PCI2 Type Description I/O, PD 3.3V-tolerant input for CPU frequency selection/33-MHz clock output. Internal 150k pull-down Intel Type-3A output buffer Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications I/O, PU 3.3V-tolerant input for CPU frequency selection/33-MHz clock output. Internal 150k pull-up Intel Type-3A output buffer Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications PWR 3.3V power supply for outputs. I/O, PU 3.3V-tolerant input for CPU clock output buffer type selection/33-MHz clock output. Internal 150k pull-up Intel Type-3A output buffer Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications 0 = K8 CPU buffer type, 1=P4 CPU buffer type. clock output buffers, can be individually enabled or disabled. The registers associated with the Serial Data Interface initialize to their default setting upon power-up, and therefore use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. The interface cannot be used during system operation for power management functions.
54
*FSB/PCI3
55 56
VDDPCI *SELP4_K8/PCI3
Frequency Select Pins (FS[D:A])
Host clock frequency selection is achieved by applying the appropriate logic levels to FS_A, FS_B, FS_C, and FS_D inputs prior to VTT_PWRGD# assertion (as seen by the clock synthesizer). Upon VTT_PWRGD# being sampled LOW by the clock chip (indicating processor VTT voltage is stable), the clock chip samples the FS_A, FS_B, FS_C, and FS_D input values. For all logic levels of FS_A, FS_B, FS_C, FS_D and FS_E, VTT_PWRGD# employs a one-shot functionality in that once a valid LOW on VTT_PWRGD# has been sampled, all further VTT_PWRGD#, FS_A, FS_B, FS_C, and FS_D transitions will be ignored, except in test mode.
Data Protocol
The clock driver serial protocol accepts byte write, byte read, block write, and block read operations from the controller. For block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For byte write and byte read operations, the system controller can access individually indexed bytes. The offset of the indexed byte is encoded in the command code, as described in Table 1.
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions, such as individual
Figure 1. CPU and SRC Frequency Select Tables
FSD
FSC
FSB
FSA CPU0 266.667 133.333 200 166.667 333.333 100 400 200 266.667 133.333 200 166.667 333.333 100 400 200 CPU1 266.667 133.333 200 166.667 333.333 100 400 250 266.667 133.333 200 166.667 333.333 100 400 250 SRC 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 LINK 66.6667 66.6667 66.6667 66.6667 66.6667 66.6667 66.6667 66.6667 133.333 133.333 133.333 133.333 133.333 133.333 133.333 133.333 PCI 33.3333 33.3333 33.3333 33.3333 33.3333 33.3333 33.3333 33.3333 33.3333 33.3333 33.3333 33.3333 33.3333 33.3333 33.3333 33.3333
FSEL3 FSEL2 FSEL1 FSEL0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Frequency Table (ROM) CPU PLL Gear CPU CPU CPU VCO Constant M N (G) 800 800 800 666.67 666.67 800 800 1000 800 800 800 666.67 666.67 800 800 1000 80 40 60 60 120 30 120 60 80 40 60 60 120 30 120 60 60 60 60 63 63 60 60 60 60 60 60 63 63 60 60 60 200 200 200 175 175 200 200 250 200 200 200 175 175 200 200 250
PCIE VCO 800 800 800 800 800 800 800 800 800 800 800 800 800 800 800 800
SRC PLL Gear Constant 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30
PCIE M 60 60 60 60 60 60 60 60 60 60 60 60 60 60 60 60
PCIE N 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200
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CY28551-3
The block write and block read protocol is outlined in Table 2 while Table 3 outlines the corresponding byte write and byte read protocol. The slave receiver address is 11010010 (D2h). Table 1. Command Code Definition Bit 7 (6:0) Description 0 = Block read or block write operation, 1 = Byte read or byte write operation Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000'
Table 2. Block Read and Block Write Protocol Block Write Protocol Bit 1 8:2 9 10 18:11 19 27:20 28 36:29 37 45:38 46 .... .... .... .... Start Slave address - 7 bits Write Acknowledge from slave Command Code - 8 bits Acknowledge from slave Byte Count - 8 bits (Skip this step if I2C_EN bit set) Acknowledge from slave Data byte 1 - 8 bits Acknowledge from slave Data byte 2 - 8 bits Acknowledge from slave Data Byte/Slave Acknowledges Data Byte N - 8 bits Acknowledge from slave Stop Description Bit 1 8:2 9 10 18:11 19 20 27:21 28 29 37:30 38 46:39 47 55:48 56 .... .... .... .... Table 3. Byte Read and Byte Write Protocol Byte Write Protocol Bit 1 8:2 9 10 18:11 19 27:20 28 29 Start Slave address - 7 bits Write Acknowledge from slave Command Code - 8 bits Acknowledge from slave Data byte - 8 bits Acknowledge from slave Stop Description Bit 1 8:2 9 10 18:11 19 20 27:21 28 Start Slave address - 7 bits Write Acknowledge from slave Command Code - 8 bits Acknowledge from slave Repeated start Slave address - 7 bits Read Page 5 of 29 Byte Read Protocol Description Start Slave address - 7 bits Write Acknowledge from slave Command Code - 8 bits Acknowledge from slave Repeat start Slave address - 7 bits Read = 1 Acknowledge from slave Byte Count from slave - 8 bits Acknowledge Data byte 1 from slave - 8 bits Acknowledge Data byte 2 from slave - 8 bits Acknowledge Data bytes from slave/Acknowledge Data Byte N from slave - 8 bits NOT Acknowledge Stop Block Read Protocol Description
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Table 3. Byte Read and Byte Write Protocol (continued) Byte Write Protocol Bit Description Bit 29 37:30 38 39 Byte Read Protocol Description Acknowledge from slave Data from slave - 8 bits NOT Acknowledge Stop
Control Registers
Byte 0: Control Register 0 Bit 7 6 5 4 3 2 1 0 @Pup 1 1 1 1 1 1 1 1 Type R/W R/W R/W R/W R/W R/W R/W R/W Name Reserved PCIEX[T/C]6 PCIEX[T/C]5 PCIEX[T/C]4 PCIEX[T/C]3 PCIEX[T/C]2 Reserved Reserved PCIEX[T/C]6 Output Enable 0 = Disable (Tri-state), 1 = Enable PCIEX[T/C]5 Output Enable 0 = Disable (Tri-state), 1 = Enable PCIEX[T/C]4 Output Enable 0 = Disable (Tri-state), 1 = Enable PCIEX[T/C]3 Output Enable 0 = Disable (Tri-state), 1 = Enable PCIEX[T/C]2 Output Enable 0 = Disable (Tri-state), 1 = Enable Reserved Description
SATA/PCIEX[T/C]0 SATA/PCIEX[T/C]0 Output Enable 0 = Disable (Tri-state), 1 = Enable
Byte 1: Control Register 1 Bit 7 6 5 4 3 2 1 0 @Pup 1 1 1 1 1 1 1 1 Type R/W R/W R/W R/W R/W R/W R/W R/W Name SATA/DOT96] 24_48M 48M REF2 REF1 REF0 CPU[T/C]1 CPU[T/C]0 Description SATA/DOT96Output Enable 0 = Disable (Tri-state), 1 = Enable 24_48M Output Enable 0 = Disabled, 1 = Enabled 48M Output Enable 0 = Disabled, 1 = Enabled REF2 Output Enable 0 = Disabled, 1 = Enabled REF1 Output Enable 0 = Disabled, 1 = Enabled REF0 Output Enable 0 = Disabled, 1 = Enabled CPU[T/C]1 Output Enable 0 = Disable (Tri-state), 1 = Enabled CPU[T/C]0 Output Enable 0 = Disable (Tri-state), 1 = Enabled
Byte 2: Control Register 2 Bit 7 6 @Pup 1 1 Type R/W R/W Name Reserved Reserved Reserved Reserved Page 6 of 29 Description
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Byte 2: Control Register 2 (continued) Bit 5 4 3 2 1 0 @Pup 1 1 1 1 1 1 Type R/W R/W R/W R/W R/W R/W Name PCI5 PCI4 PCI3 PCI2 PCI1 PCI0 PCI5 Output Enable 0 = Disabled, 1 = Enabled PCI4 Output Enable 0 = Disabled, 1 = Enabled PCI3 Output Enable 0 = Disabled, 1 = Enabled PCI2 Output Enable 0 = Disabled, 1 = Enabled PCI1 Output Enable 0 = Disabled, 1 = Enabled PCI0 Output Enable 0 = Disabled, 1 = Enabled Description
Byte 3: Control Register 3 Bit 7 6 5 4 3 2 1 0 @Pup 1 1 1 1 0 1 1 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Name LINK1 LINK0 Reserved Reserved Reserved PCI REF 48M, 24_48M LINK1 Output Enable 0 = Disabled, 1 = Enabled LINKI0 Output Enable 0 = Disabled, 1 = Enabled Reserved Reserved Reserved 33-MHz Output Drive Strength 0 = 2x, 1 = 1x REF Output Drive Strength 0 = 2x, 1 = 1x 48-MHz and 24_48M Output Drive Strength 0 = 2x, 1 = 1x Description
Byte 4: Control Register 4 Bit 7 @Pup 0 Type R/W Name CPU1 Description Allow control of CPU1 with assertion of CPU_STP# 0 = Free Running 1 = Stopped with CPU_STP# Allow control of CPU0 with assertion of CPU_STP# 0 = Free Running 1= Stopped with CPU_STP# Reserved Allow control of PCIEX with assertion of PCI_STP# 0 = Free Running 1 = Stopped with PCI_STP# SW Frequency selection bits. See Figure 1.
6
0
R/W
CPU0
5 4
0 0
R/W R/W
Reserved PCIEX
3 2 1 0
0 0 0 0
R/W R/W R/W R/W
FSEL_D FSEL_C FSEL_B FSEL_A
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Byte 5: Control Register 5 Bit 7 6 @Pup 0 0 Type R/W R/W Name CPU_SS1 CPU_SS0 Description CPU (PLL1) Spread Spectrum Selection 00: -0.5% (peak to peak) 01: 0.25% (peak to peak) 10: -1.0% (peak to peak) 11: 0.5% (peak to peak) PLL1 (CPUPLL) Spread Spectrum Enable 0 = Spread off, 1 = Spread on. PLL2 (PCIEPLL) Spread Spectrum Selection 0: -0.5% (peak to peak) 0: -1.0% (peak to peak) PLL2 (PCIEPLL) Spread Spectrum Enable 0: SRC spread off, 1: SRC spread on. PLL3 (SATAPLL) Spread Spectrum Enable 0 = Spread off, 1 = Spread on 24M/48-MHz output selection 0 = 48 MHz, 1 = 24 MHz Reserved
5 4
0 0
R/W R/W
CPU_SS_OFF PCIE_SS0
3 2 1 0
0 0 HW 0
R/W R/W R/W R/W
PCIE_SS_OFF SATA_SS_OFF SEL24_48 Reserved
Byte 6: Control Register 6 Bit 7 @Pup 0 Type R/W Name SW_RESET Description Software Reset. When set, the device will assert a reset signal on SRESET# upon completion of the block/word/byte write that set it. After asserting and deasserting the SRESET# this bit will self clear (set to 0). Reserved LINK and PCI clock source selection 0 = PLL2(SRCPLL), 1 = PLL3 (SATAPLL) FSD Reflects the value of the FSD pin sampled on power-up. 0 = FSD was low during VTT_PWRGD# assertion. FSC Reflects the value of the FSC pin sampled on power-up. 0 = FSC was low during VTT_PWRGD# assertion. FSB Reflects the value of the FSB pin sampled on power-up 0 = FSB was LOW during VTT_PWRGD# assertion. FSA Reflects the value of the FSA pin sampled on power-up. 0 = FSA was LOW during VTT_PWRGD# assertion Power Status bit: 0 = Internal power or Internal resets are NOT valid 1 = Internal power and Internal resets are valid Read only Bit 7 sets to 0 when Bit 7 =0
6 5 4 3 2 1 0
0 0 HW HW HW HW HW
R/W R/W R R R R R
Reserved FIX_LINK_PCI FSD FSC FSB FSA POWERGOOD
Byte 7: Vendor ID Bit 7 6 5 4 3 2 1 @Pup 0 0 0 0 1 0 0 Type R R R R R R R Name Revision Code Bit 3 Revision Code Bit 3 Revision Code Bit 2 Revision Code Bit 2 Revision Code Bit 1 Revision Code Bit 1 Revision Code Bit 0 Revision Code Bit 0 Vendor ID Bit 3 Vendor ID Bit 2 Vendor ID Bit 1 Vendor ID Bit 3 Vendor ID Bit 2 Vendor ID Bit 1 Description
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Byte 7: Vendor ID (continued) Bit 0 @Pup 0 Type R Name Vendor ID Bit 0 Vendor ID Bit 0 Description
Byte 8: Control Register 8 Bit 7 6 @Pup 0 0 Type R/W R/W Name RESERVED CR1_PCIEX6 RESERVED, Set = 0 PCIEX[T/C]6 CLKREQ#A Control 1 = PCIEX [T/C]6 stoppable by CLKREQ#A pin 0 = Free running PCIEX[T/C]5 CLKREQ#B Control 1 = PCIEX [T/C]5 stoppable by CLKREQ#B pin 0 = Free running PCIEX[T/C]4 CLKREQ#B Control 1 = PCIEX [T/C]4 stoppable by CLKREQ#B pin 0 = Free running RESERVED, Set = 0 RESERVED, Set = 0 RESERVED, Set = 0 RESERVED, Set = 0 Description
5
0
R/W
CR1_PCIEX5
4
0
R/W
CR1_PCIEX4
3 2 1 0
0 0 0 0
R/W R/W R/W R/W
RESERVED RESERVED RESERVED RESERVED
Byte 9: Control Register 9 Bit 7 6 5 4 3 2 @Pup 0 0 0 0 0 0 Type R/W R/W R/W R/W R/W R/W Name DF3_N8 DF2_N8 DF1_N8 RESERVED RESERVED SMSW_Bypass Description The DF3_N[8:0] will be used to configure CPU frequency for Dynamic Frequency. DOC[1:2] =11 The DF2_N[8:0] will be used to configure CPU frequency for Dynamic Frequency. DOC[1:2] =10 The DF1_N[8:0] will be used to configure CPU frequency for Dynamic Frequency. DOC[1:2] =01 RESERVED, Set = 0 RESERVED, Set = 0 Smooth switch Bypass 0: Activate SMSW block 1: Bypass and de-activate SMSW block. Smooth switch select 0: select CPU_PLL 1: select SRC_PLL. RESERVED, Set = 0
1
0
R/W
SMSW_SEL
0
0
R/W
RESERVED
Byte 10: Control Register 10 Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Name DF1_N7 DF1_N6 DF1_N5 DF1_N4 DF1_N3 DF1_N2 DF1_N1 DF1_N0 Description The DF1_N[8:0] will be used to configure CPU frequency for Dynamic Frequency. DOC[1:2] =01.
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Byte 11: Control Register 11 Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Name DF2_N7 DF2_N6 DF2_N5 DF2_N4 DF2_N3 DF2_N2 DF2_N1 DF2_N0 Description The DF2_N[8:0] will be used to configure CPU frequency for Dynamic Frequency. DOC[1:2] =10
Byte 12: Control Register 12 Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Name DF3_N7 DF3_N6 DF3_N5 DF3_N4 DF3_N3 DF3_N2 DF3_N1 DF3_N0 Description The DF3_N[8:0] will be used to configure CPU frequency for Dynamic Frequency. DOC[1:2] =11
Byte 13: Control Register 13 Bit 7 @Pup 0 Type R/W Name Description Recovery_Frequency This bit allows selection of the frequency setting that the clock will be restored to once the system is rebooted 0: Use HW settings, 1: Recovery N[8:0] Timer_SEL Timer_SEL selects the WD reset function at the SRESET pin when WD times out. 0 = Reset and Reload Recovery_Frequency 1 = Only Reset Time_Scale allows selection of WD time scale 0 = 294 ms 1 = 2.34 s WD_Alarm is set to "1" when the watchdog times out. It is reset to "0" when the system clears the WD_TIMER time stamp. Watchdog timer time stamp selection 000: Reserved (test mode) 001: 1 * Time_Scale 010: 2 * Time_Scale 011: 3 * Time_Scale 100: 4 * Time_Scale 101: 5 * Time_Scale 110: 6 * Time_Scale 111: 7 * Time_Scale Watchdog timer enable, when the bit is asserted, Watchdog timer is triggered and time stamp of WD_Timer is loaded 0 = Disable, 1 = Enable
6
0
R/W
5 4 3 2 1
1 0 0 0 0
R/W R/W R/W R/W R/W
Time_Scale WD_Alarm WD_TIMER2 WD_TIMER1 WD_TIMER0
0
0
R/W
WD_EN
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Byte 14: Control Register 14 Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Name CPU_DAF_N7 CPU_DAF_N6 CPU_DAF_N5 CPU_DAF_N4 CPU_DAF_N3 CPU_DAF_N2 CPU_DAF_N1 CPU_DAF_N0 Description If Prog_CPU_EN is set, the values programmed in CPU_DAF_N[8:0] and CPU_DAF_M[6:0] will be used to determine the CPU output frequency. The setting of the FS_Override bit determines the frequency ratio for CPU and other output clocks. When it is cleared, the same frequency ratio stated in the Latched FS[E:A] register will be used. When it is set, the frequency ratio stated in the FSEL[3:0] register will be used.
Byte 15: Control Register 15 Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Name CPU_DAF_N8 CPU_DAF_M6 CPU_DAF_M5 CPU_DAF_M4 CPU_DAF_M3 CPU_DAF_M2 CPU_DAF_M1 CPU_DAF_M0 Description If Prog_CPU_EN is set, the values programmed in CPU_DAF_N[8:0] and CPU_DAF_M[6:0] will be used to determine the CPU output frequency. The setting of the FS_Override bit determines the frequency ratio for CPU and other output clocks. When it is cleared, the same frequency ratio stated in the Latched FS[E:A] register will be used. When it is set, the frequency ratio stated in the FSEL[3:0] register will be used.
Byte 16: Control Register 16 Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Name PCIE_DAF_N7 PCIE_DAF_N6 PCIE_DAF_N5 PCIE_DAF_N4 PCIE_DAF_N3 PCIE_DAF_N2 PCIE_DAF_N1 PCIE_DAF_N0 Description The PCIE_DAF_N[8:0] will be used to configure PCIE frequency for Dial-A Frequency
Byte 17: Control Register 17 Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Name Recovery N7 Recovery N6 Recovery N5 Recovery N4 Recovery N3 Recovery N2 Recovery N1 Recovery N0 Watchdog Recovery Bit Watchdog Recovery Bit Watchdog Recovery Bit Watchdog Recovery Bit Watchdog Recovery Bit Watchdog Recovery Bit Watchdog Recovery Bit Watchdog Recovery Bit Description
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Byte 18: Control Register 18 Bit 7 6 @Pup 0 0 Type R/W R/W Name PCIE_N8 FS[D:A] Description PCI-E Dial-A-Frequency Bit N8 FS_Override 0 = Select operating frequency by FS(D:A) input pins 1 = Select operating frequency by FSEL_(3:0) settings Dynamic Frequency for CPU frequency Enable 0 = Disable, 1 = Enable RESET_I# Enable 0: Disable, 1: Enable. Programmable SRC frequency enable 0 = Disabled, 1 = Enabled. Programmable CPU frequency enable 0 = Disabled, 1 = Enabled. Watchdog Autorecovery Mode 0 = Disable (Manual), 1= Enable (Auto) Watchdog Recovery Bit
5 4 3 2 1 0
0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W
DF_EN RESET_I_EN Prog_PCIE_EN Prog_CPU_EN Watchdog Autorecovery Recovery N8
Table 4. Crystal Recommendations Frequency (Fund) 14.31818 MHz Cut AT Loading Load Cap Parallel 20 pF Drive (max.) 0.1 mW Shunt Cap (max.) 5 pF Motional (max.) 0.016 pF Tolerance (max.) 35 ppm Stability (max.) 30 ppm Aging (max.) 5 ppm
Crystal Recommendations
The CY28551-3 requires a Parallel Resonance Crystal. Substituting a series resonance crystal will cause the CY28551-3 to operate at the wrong frequency and violate the ppm specification. For most applications there is a 300-ppm frequency shift between series and parallel crystals due to incorrect loading.
Figure 2. Crystal Capacitive Clarification
Crystal Loading
Crystal loading plays a critical role in achieving low ppm performance. To realize low ppm performance, the total capacitance the crystal will see must be considered to calculate the appropriate capacitive loading (CL). Figure 2 shows a typical crystal configuration using the two trim capacitors. An important clarification for the following discussion is that the trim capacitors are in series with the crystal not parallel. It's a common misconception that load capacitors are in parallel with the crystal and should be approximately equal to the load capacitance of the crystal. This is not true.
Calculating Load Capacitors
In addition to the standard external trim capacitors, trace capacitance and pin capacitance must also be considered to correctly calculate crystal loading. As mentioned previously, the capacitance on each side of the crystal is in series with the crystal. This means the total capacitance on each side of the crystal must be twice the specified crystal load capacitance (CL). While the capacitance on each side of the crystal is in series with the crystal, trim capacitors (Ce1,Ce2) should be calculated to provide equal capacitive loading on both sides.
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Figure 3. Crystal Loading Example
Dynamic Frequency
Dynamic Frequency - Dynamic Frequency (DF) is a technique to increase CPU frequency or SRC frequency dynamically from any starting value. The user selects the starting point, either by HW, FSEL, or DAF, then enables DF. After that, DF will dynamically change as determined by DF-N registers.
Clock Chip
Ci1
Ci2
Pin 3 to 6p
DF Pin - There are two pins to be used for Dynamic Frequency (DF). When used as DF, these two pins will map to four DF-N registers that correspond to different "N" values for Dynamic Frequency. Any time there is a change in DF, it should load the new value.
DOC[2:1] DOC N register Original Frequency DF1_N DF2_N DF3_N
Cs1
X1
X2
Cs2
Trace 2.8 pF
00 01 10 11
XTAL
Ce1 Ce2
Trim 33 pF
DF_EN bit - This bit enables the DF mode. By default, it is not set. When set, the operating frequency is determined by DF[2:0] pins. Default = 0, (No DF)
Use the following formulas to calculate the trim capacitor values for Ce1 and Ce2.
Load Capacitance (each side) Ce = 2 * CL - (Cs + Ci) Total Capacitance (as seen by the crystal) CLe
Dial-A-Frequency (CPU & PCIEX)
This feature allows the user to over clock their system by slowly stepping up the CPU or SRC frequency. When the programmable output frequency feature is enabled, the CPU and SRC frequencies are determined by the following equation: Fcpu = G * N/M or Fcpu=G2 * N, where G2 = G/M. "N" and "M" are the values programmed in Programmable Frequency Select N-Value Register and M-Value Register, respectively. "G" stands for the PLL Gear Constant, which is determined by the programmed value of FS[E:A]. See Figure 1 for the Gear Constant for each Frequency selection. The PCI Express only allows user control of the N register, the M value is fixed and documented in Figure 1. In this mode, the user writes the desired N and M value into the DAF I2C registers. The user cannot change only the M value and must change both the M and the N values at the same time, if they require a change to the M value. The user may change only the N value if required. Associated Register Bits CPU_DAF Enable - This bit enables CPU DAF mode. By default, it is not set. When set, the operating frequency is determined by the values entered into the CPU_DAF_N register. Note: the CPU_DAF_N and M register must contain valid values before CPU_DAF is set. Default = 0, (No DAF). CPU_DAF_N - There are nine bits (for 512 values) to linearly change the CPU frequency (limited by VCO range). Default = 0, (0000). The allowable values for N are detailed in the frequency select table in Figure 1. CPU DAF M - There are 7 bits (for 128 values) to linearly change the CPU frequency (limited by VCO range). Default = 0, the allowable values for M are detailed in the frequency select table in Figure 1.
=
1 ( Ce1 + Cs1 + Ci1 +
1
1 Ce2 + Cs2 + Ci2
)
CL ................................................... Crystal load capacitance CLe ........................................ Actual loading seen by crystal using standard value trim capacitors Ce .................................................... External trim capacitors Cs.............................................. Stray capacitance (terraced) Ci ........................................................... Internal capacitance (lead frame, bond wires etc.)
Multifunction Pin Selection
In CY28551-3, some of the pins can provide different types of frequency, depending on the SEL[1:0] HW strapping pin setting, to support different chipset vendors. The configuration is shown as follows: SEL[1:0] 00 01 10 11 LINK/DOT/SA TA LINK DOT LINK SATA SATA/PCIE SATA SATA PCIEX PCIEX Platform SIS Intel W/Gfx VIA Intel
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SRC_DAF Enable - This bit enables SRC DAF mode. By default, it is not set. When set, the operating frequency is determined by the values entered into the SRC_DAF_N register. Note: the SRC_DAF_N register must contain valid values before SRC_DAF is set. Default = 0, (No DAF). SRC_DAF_N - There are nine bits (for 512 values) to linearly change the CPU frequency (limited by VCO range). Default = 0, (0000). The allowable values for N are detailed in the frequency select table in Figure 1. Recovery - The recovery mechanism during CPU DAF when the system locks up and the watchdog timer is enabled is determined by the "Watchdog Recovery Mode" and "Watchdog Auto recovery Enable" bits. The possible recovery methods are (A) Auto, (B) Manual (by Recovery N), (C) HW, and (D) No recovery - just send reset signal. There is no recovery mode for SRC Dial a frequency.
It is not recommended to enable over-clocking and change the N values of both PLLs in the same SMBUS block write and use smooth switch mechanism on spread spectrum on/off.
Watchdog Timer
The Watchdog timer is used in the system in conjunction with overclocking. It is used to provide a reset to a system that has hung up due to overclocking the CPU and the Front side bus. The watchdog is enabled by the user and if the system completes its checkpoints, the system will clear the timer. However, when the timer runs out, there will be a reset pulse generated on the SRESET# pin for 20 ms that is used to reset the system. When the Watchdog is enabled (WD_EN = 1) the Watchdog timer will start counting down from a value of Watchdog_timer * time scale. If the Watchdog timer reaches 0 before the WD_EN bit is cleared then it will assert the SRESET# signal and set the Watchdog Alarm bit to 1. To use the watchdog the SRESET# pin must be enabled by SRESET_EN pin being sampled LOW by VTTPWRGD# assertion during system boot up. At any point if during the Watchdog timer countdown, if the time stamp or Watchdog timer bits are changed the timer will reset and start counting down from the new value. After the Reset pulse, the watchdog will stay inactive until either: 1. A new time stamp or watchdog timer value is loaded. 2. The WD_EN bit is cleared and then set again. Watchdog Register Bits The following register bits are associated with the Watchdog timer: Watchdog Enable - This bit (by default) is not set, which disables the Watchdog. When set, the Watchdog is enabled. Also, when there is a transition from LOW to HIGH, the timer reloads. Default = 0, disable Watchdog Timer - There will be three bits (for seven combinations) to select the timer value. Default = 000, the value '000' is a reserved test mode. Watchdog Alarm - This bit is a flag and when it is set, it indicates that the timer has expired. This bit is not set by default. When the bit is set, the user is allowed to clear. Default = 0. Watchdog Time Scale - This bit selects the multiplier. When this bit is not set, the multiplier will be 250 ms. When set (by default), the multiplier will be 3s. Default = 1 Watchdog Reset Mode - This selects the Watchdog Reset Mode. When this bit is not set (by default), the Watchdog will send a reset pulse and reload the recovery frequency depends on Watchdog Recovery Mode setting. When set, it just send a reset pulse.Default = 0, Reset & Recover Frequency. Watchdog Recovery Mode - This bit selects the location to recover from. One option is to recover from the HW settings (already stored in SMBUS registers for readback capability) and the second is to recover from a register called "Recovery N". Default = 0 (Recover from the HW setting)
Software Frequency Select
This mode allows the user to select the CPU output frequencies using the Software Frequency select bits in the SMBUS register. FSEL - There will be four bits (for 16 combinations) to select predetermined CPU frequencies from a table. The table selections are detailed in Figure 1. FS_Override - This bit allows the CPU frequency to be selected from HW or FSEL settings. By default, this bit is not set and the CPU frequency is selected by HW. When this bit is set, the CPU frequency is selected by the FSEL bits. Default = 0. Recovery - The recovery mechanism during FSEL when the system locks up is determined by the "Watchdog Recovery Mode" and "Watchdog Auto recovery Enable" bits. The only possible recovery method is to Hardware Settings. Auto recovery or manual recovery can cause a wrong output frequency because the output divider may have changed with the selected CPU frequency and these recovery methods will not recover the original output divider setting.
Smooth Switching
The device contains 1 smooth switch circuit that is shared by the CPU PLL and SRC PLL. The smooth switch circuit ensures that when the output frequency changes by overclocking, the transition from the old frequency to the new frequency is a slow, smooth transition containing no glitches. The rate of change of output frequency when using the smooth switch circuit is less than 1 MHz/0.667 s. The frequency overshoot and undershoot will be less than 2%. The Smooth Switch circuit can be assigned auto or manual. In Auto mode, clock generator will assign smooth switch automatically when the PLL will do overclocking. For manual mode, the smooth switch circuit can be assign to either PLL via Smbus. By default the smooth switch circuit is set to auto mode. Either PLL can still be over-clocked when it does not have control of the smooth switch circuit but it is not guaranteed to transition to the new frequency without large frequency glitches.
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Watchdog Autorecovery Enable - This bit by default is set and the recovered values are automatically written into the "Watchdog Recovery Register" and reloaded by the Watchdog function. When this bit is not set, the user is allowed to write to the "Watchdog Recovery Register". The value stored in the "Watchdog Recovery Register" will be used for recovery. Default = 1, Autorecovery. Watchdog Recovery Register - This is a nine-bit register to store the watchdog N recovery value. This value can be written by the Auto recovery or User depending on the state of the "Watchdog Auto Recovery Enable bit".
PD Clarification
The VTT_PWRGD#/PD pin is a dual-function pin. During initial power-up, the pin functions as VTT_PWRGD#. Once VTT_PWRGD# has been sampled LOW by the clock chip, the pin assumes PD functionality. The PD pin is an asynchronous active HIGH input used to shut off all clocks cleanly prior to shutting off power to the device. This signal needs to be synchronized internal to the device prior to powering down the clock synthesizer. PD is also an asynchronous input for powering up the system. When PD is asserted HIGH, all clocks need to be driven to a LOW value and held prior to turning off the VCOs and the crystal oscillator PD Assertion When PD is sampled HIGH by two consecutive rising edges of CPUC, all single-ended outputs must be held LOW on their next HIGH-to-LOW transition and differential clocks must held HIGH or tri-stated (depending on the state of the control register drive mode bit) on the next diff clock# HIGH-to-LOW transition within 4 clock periods. When the SMBus PD drive mode bit corresponding to the differential (CPU, SRC, and DOT) clock output of interest is programmed to '0', the clock output must be held with "Diff clock" pin driven HIGH at 2 x Iref, and "Diff clock#" tri-state. If the control register PD drive mode bit corresponding to the output of interest is programmed to "1", then both the "Diff clock" and the "Diff clock#" are tri-state. Note Figure 4 shows CPUT = 133 MHz and PD drive mode = '1' for all differential outputs. This diagram and description is applicable to valid CPU frequencies 100, 133, 166, and 200 MHz. In the event that PD mode is desired as the initial power-on state, PD must be asserted HIGH in less than 10 s after asserting Vtt_PwrGd#. PD Deassertion The power-up latency needs to be less than 1.8 ms. This is the time from the deassertion of the PD pin or the ramping of the power supply until the time that stable clocks are output from the clock chip. All differential outputs stopped in a tri-state condition resulting from power-down must be driven HIGH in less than 300 s of PD deassertion to a voltage greater than 200 mV. After the clock chip's internal PLL is powered up and locked, all outputs are to be enabled within a few clock cycles of each other. Figure 5 is an example showing the relationship of clocks coming up. Unfortunately, we can not show all possible combinations, designers need to insure that from the first active clock output to the last takes no more than two full PCI clock cycles. CPU_STP# Clarification The CPU_STP# signal is an active low input used for cleanly stopping and starting the CPU outputs while the rest of the clock generator continues to function. Note that the assertion and de-assertion of this signal is absolutely asynchronous. CPU_STP# Assertion The CPU_STP# signal is an active low input used for synchronous stopping and starting the CPU output clocks while the rest of the clock generator continues to function. When the CPU_STP# pin is asserted, all CPU outputs that are set with the SMBus configuration to be stoppable via assertion of CPU_STP# will be stopped after being sampled by 2-6 rising edges of the internal CPUC clock. The final state of the Page 15 of 29
Watchdog Recovery Modes
There are three operating modes that require Watchdog recovery. The modes are Dial-A-Frequency (DAF), Dynamic Clocking (DF), or Frequency Select. There are 4 different recovery modes: the following sections list the operating mode and the recovery mode associated with it. Recover to Hardware M, N, O When this recovery mode is selected, in the event of a Watchdog timeout, the original M, N, and O values that were latched by the HW FSEL pins at chip boot-up should be reloaded. Autorecovery When this recovery mode is selected, in the event of a Watchdog timeout, the M and N values stored in the Recovery M and N registers should be reloaded. The current values of M and N will be latched into the internal recovery M and N registers by the WD_EN bit being set. Manual Recovery When this recovery mode is selected, in the event of a Watchdog timeout, the N value as programmed by the user in the N recovery register, and the M value that is stored in the Recovery M register (not accessible by the user) should be restored. The current M value should be latched M recovery register by the WD_EN bit being set. No Recovery If no recovery mode is selected, in the event of a Watchdog time out, the device should just assert the SRESET# and keep the current values of M and N
Software Reset
Software reset is a reset function that is used to send out a pulse from the SRESET# pin. It is controlled by the SW_RESET enable register bit. Upon completion of the byte/word/block write in which the SW_RESET bit was set, the device will send a RESET pulse on the SRESET# pin. The duration of the SRESET# pulse should be the same as the duration of the SRESET# pulse after a Watchdog timer time out. After the SRESET# pulse is asserted the SW_RESET bit should be automatically cleared by the device.
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Figure 4. PD Assertion Timing Waveform
PD C PU T, 133M H z C PU C , 133M H z
SRC T 100M H z
SRC C 100M H z
L IN K
U SB , 48M H z
DO T96T
D O T96C
P C I, 3 3 M H z
REF
Figure 5. PD Deassertion Timing Waveform
T s ta b le < 1 .8 m s
PD
C PU T, 133M H z
C PU C , 133M H z
SR C T 100M H z
SR C C 100M H z
L IN K
U SB, 48M H z
D O T96T
D O T96C
P C I, 3 3 M H z
REF
T d r iv e _ P W R D N # <300 s, > 200 m V
stopped CPU clock is Low due to tristate, both CPUT and CPUC outputs will not be driven. PU_STP# De-Assertion The de-assertion of the CPU_STP# signal will cause all CPU outputs that were stopped to resume normal operation in a synchronous manner. Synchronous manner meaning that no short or stretched clock pulses will be produce when the clock resumes. The maximum latency from the de-assertion to active outputs is between 2-6 CPU clock periods (2 clocks are shown). If the control register tristate bit corresponding to the output of interest is programmed to '1', then the stopped CPU outputs will be driven high within 10ns of CPU_Stop# de-assertion to a voltage greater than 200mV
PCI_STP# Clarification The PCI_STP# signal is an active low input used for cleanly stopping and starting the PCI and PCIEX outputs while the rest of the clock generator continues to function. The PCIF and PCIEX clocks are special in that they can be programmed to ignore PCI_STP# by setting the register bit corresponding to the output of interest to free running. Outputs set to free running will ignore both the PCI_STP# pin. PCI_STP# Assertion The impact of asserting the PCI_STP# signal will be the following. The clock chip is to sample the PCI_STP# signal on a rising edge of PCIF clock. After detecting the PCI_STP# assertion low, all PCI and stoppable PCIF clocks will latch low Page 16 of 29
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on their next high to low transition. After the PCI clocks are latched low, the stoppable PCIEX clocks will latch to low due to tristate as show below. The one PCI clock latency as shown is critical to system functionality, any violation of this may result in system failure. The Tsu_pci_stp# is the setup time required by the clock generator to correctly sample the PCI_STP# assertion, this time is 10 ns minimum. PCI_STP# De-Assertion The de-assertion of the PCI_STP# signal is to function as follows. The de-assertion of the PCI_STP# signal is to be sampled on the rising edge of the PCIF free running clock domain. After detecting PCI_STP# de-assertion, all PCI, stoppable PCIF and Stoppable PCIEX clocks will resume in a glitch free manner. The PCI and PCIEX clock resume latency should exactly match the 1 PCI clock latency required for PCI_STP# entry. The stoppable PCIEX clocks must be driven high within 15ns of PCI_STP# de-assertion. The drawing below shows the appropriate relationship. The Tsu_cpu_stp# is the setup time required by the clock generator to correctly sample the PCI_STP# de-assertion, this time is 10 ns minimum. CLKREQ# Clarification The CLKREQ# signals are active low input used for clean stopping and starting selected SRC outputs. The outputs controlled by CLKREQ# are determined by the settings in register bytes 10 and 11. The CLKREQ# signal is a
de-bounced signal in that its state must remain unchanged during two consecutive rising edges of DIFC to be recognized as a valid assertion or de-assertion. (The assertion and de-assertion of this signal is absolutely asynchronous) CLKREQ# Assertion All differential outputs that were stopped are to resume normal operation in a glitch free manner. The maximum latency from the de-assertion to active outputs is between 2-6 PCIEX clock periods (2 clocks are shown) with all CLKREQ# outputs resuming simultaneously. If the CLKREQ# drive mode is tristate, the all stopped PCIEX outputs must be driven high within 10 ns of CLKREQ# de-assertion to a voltage greater than 200mV CLKREQ# De-Assertion The impact of asserting the CLKREQ# pins is all DIF outputs that are set in the control registers to stoppable via assertion of CLKREQ# are to be stopped after their next transition. When the control register CLKREQ# drive mode bit is programmed to '0', the final state of all stopped PCIEX signals is PCIEXT clock = High and PCIEXC = Low. There is to be no change to the output drive current values, SRCT will be driven high with a current value equal 6 x Iref, When the control register CLKREQ# drive mode bit is programmed to '1', the final state of all stopped DIF signals is low, both PCIEXT clock and PCIEXC clock outputs will not be driven.
Figure 6. CPU_STP# Assertion Timing waveform
CPU_STP# CPUT CPUC
Figure 7. CPU_STP# De-Assertion
CPU_STP# CPUT CPUC C P U T In t e r n a l
C P U C In t e r n a l
T d r iv e _ C P U _ S T P # , 1 0 n S > 2 0 0 m V
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Figure 8. PCI_STP# Assertion
P C I_ S T P # P C I_ F
Tsu _ p c i_ stp # > 1 0 ns
PC I P C IE X 1 00 M H z
Figure 9. PCI_STP# De-Assertion
Tdrive_PCIEX <15 ns
PCI_STP# PCI_F
PCI PCIEX 100MHz
Figure 10. CLKREQ# De-Assertion
PE_REQ#
PCIEXT(free running) PCIEXC(free running) PCIEXT(stoppable)
Tdrive_PE_REQ# < 10ns
PCIEXC(stoppable)
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Figure 11. VTT_PWRGD# Timing Diagram
S1
S2
Delay > 0.25 ms
VDD_A = 2.0V
VTT_PWRGD# = Low
Sample Inputs straps
Wait for <1.8 ms
S0
S3
VDD_A = off
Power Off
Normal Operation
VTT_PWRGD# = toggle
Enable Outputs
Figure 12. VTT_PWRGD# Timing Diagram
FS_[D:A] VTT_PWRGD# PWRGD_VRM
VDD Clock Gen Clock State
State 0 Off Off
0.2-0.3 ms Delay
State 1
Wait for VTT_PWRGD#
Sample Sels State 2 State 3 On
Device is not affected, VTT_PWRGD# is ignored
Clock Outputs Clock VCO
On
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Absolute Maximum Conditions
Parameter VDD VDD_A VIN TS TA TJ OJC OJA ESDHBM UL-94 MSL Description Core Supply Voltage Analog Supply Voltage Input Voltage Temperature, Storage Temperature, Operating Ambient Temperature, Junction Dissipation, Junction to Case Dissipation, Junction to Ambient ESD Protection (Human Body Model) Flammability Rating Moisture Sensitivity Level Relative to VSS Non-functional Functional Functional Mil-STD-883E Method 1012.1 JEDEC (JESD 51) MIL-STD-883, Method 3015 At 1/8 in. Condition Min. -0.5 -0.5 -0.5 -65 0 - - - 2000 V-0 1 Max. 4.6 4.6 VDD + 0.5 150 70 150 20 60 - Unit V V VDC C C C C/W C/W V
Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
DC Electrical Specifications
Parameter All VDDs VILI2C VIHI2C VIL_FS VIH_FS VIL VIH IIL IIH VOL VOH IOZ CIN COUT LIN VXIH VXIL IDD3.3V IPT3.3V Description 3.3V Operating Voltage Input Low Voltage Input High Voltage FS_[A:D] Input Low Voltage FS_[A:D] Input High Voltage 3.3V Input Low Voltage 3.3V Input High Voltage Input Low Leakage Current Input High Leakage Current 3.3V Output Low Voltage 3.3V Output High Voltage High-impedance Output Current Input Pin Capacitance Output Pin Capacitance Pin Inductance Xin High Voltage Xin Low Voltage Dynamic Supply Current Power-down Supply Current At max. load and freq. per Figure 15 PD asserted, Outputs Tri-state Except internal pull-up resistors, 0 < VIN < VDD Except internal pull-down resistors, 0 < VIN < VDD IOL = 1 mA IOH = -1 mA 3.3 5% SDATA, SCLK SDATA, SCLK Condition Min. 3.135 - 2.2 VSS - 0.3 0.7 VSS - 0.3 2.0 -5 - - 2.4 -10 3 3 - 0.7VDD 0 - - Max. 3.465 1.0 - 0.35 VDD + 0.5 0.8 VDD + 0.3 - 5 0.4 - 10 5 5 7 VDD 0.3VDD 500 12 Unit V V V V V V V A A V V A pF pF nH V V mA mA
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AC Electrical Specifications
Parameter Crystal TDC TPERIOD TR/TF TCCJ LACC Description XIN Duty Cycle Condition The device will operate reliably with input duty cycles up to 30/70 but the REF clock duty cycle will not be within specification When XIN is driven from an external clock source Measured between 0.3VDD and 0.7VDD As an average over 1-s duration Over 150 ms Min. 47.5 Max. 52.5 Unit %
XIN Period XIN Rise and Fall Times XIN Cycle to Cycle Jitter Long-term Accuracy
69.841 - - - 45 9.99900 7.49925 5.99940 4.99950 3.74963 2.99970 2.49975 9.99900 7.49925 5.99940 4.99950 3.74963 2.99970 2.49975 9.91400 7.41425 5.91440 4.91450 3.66463 2.91470 2.41475 9.91400 7.41425 5.91440
71.0 10.0 500 300 55 10.0100 7.50075 6.00060 5.00050 3.75038 3.00030 2.50025 10.0100 7.50075 6.00060 5.00050 3.75038 3.00030 2.50025 10.0860 7.58575 6.08560 5.08550 3.83538 3.08530 2.58525 10.1363 7.62345 6.11576
ns ns ps ppm % ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
CPU at 0.7V (SSC refers to -0.5% spread spectrum) TDC CPUT and CPUC Duty Cycle Measured at crossing point VOX @ 0.1s TPERIOD TPERIOD TPERIOD TPERIOD TPERIOD TPERIOD TPERIOD TPERIODSS TPERIODSS TPERIODSS TPERIODSS TPERIODSS TPERIODSS TPERIODSS TPERIODAbs TPERIODAbs TPERIODAbs TPERIODAbs TPERIODAbs TPERIODAbs TPERIODAbs 100-MHz CPUT and CPUC Period 133-MHz CPUT and CPUC Period 166-MHz CPUT and CPUC Period 200-MHz CPUT and CPUC Period 266-MHz CPUT and CPUC Period 333-MHz CPUT and CPUC Period 400-MHz CPUT and CPUC Period Measured at crossing point VOX @ 0.1s Measured at crossing point VOX @ 0.1s Measured at crossing point VOX @ 0.1s Measured at crossing point VOX @ 0.1s Measured at crossing point VOX @ 0.1s Measured at crossing point VOX @ 0.1s Measured at crossing point VOX @ 0.1s
100-MHz CPUT and CPUC Period, SSC Measured at crossing point VOX @ 0.1s 133-MHz CPUT and CPUC Period, SSC Measured at crossing point VOX @ 0.1s 166-MHz CPUT and CPUC Period, SSC Measured at crossing point VOX @ 0.1s 200-MHz CPUT and CPUC Period, SSC Measured at crossing point VOX @ 0.1s 266-MHz CPUT and CPUC Period, SSC Measured at crossing point VOX @ 0.1s 333-MHz CPUT and CPUC Period, SSC Measured at crossing point VOX @ 0.1s 400-MHz CPUT and CPUC Period, SSC Measured at crossing point VOX @ 0.1s 100-MHz CPUT and CPUC Absolute period 133-MHz CPUT and CPUC Absolute period 166-MHz CPUT and CPUC Absolute period 200-MHz CPUT and CPUC Absolute period 266-MHz CPUT and CPUC Absolute period 333-MHz CPUT and CPUC Absolute period 400-MHz CPUT and CPUC Absolute period Measured at crossing point VOX @ 1 clock Measured at crossing point VOX @ 1 clock Measured at crossing point VOX @ 1 clock Measured at crossing point VOX @ 1 clock Measured at crossing point VOX @ 1 clock Measured at crossing point VOX @ 1 clock Measured at crossing point VOX @ 1 clock Measured at crossing point VOX @ 1 clock Measured at crossing point VOX @ 1 clock Measured at crossing point VOX @ 1 clock
TPERIODSSAbs 100-MHz CPUT and CPUC Absolute period, SSC TPERIODSSAbs 133-MHz CPUT and CPUC Absolute period, SSC TPERIODSSAbs 166-MHz CPUT and CPUC Absolute period, SSC
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CY28551-3
AC Electrical Specifications (continued)
Parameter Description Condition Measured at crossing point VOX @ 1 clock Measured at crossing point VOX @ 1 clock Measured at crossing point VOX @ 1 clock Measured at crossing point VOX @ 1 clock Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured differentially from 150 mV Measured single-endedly from 75 mV Math averages Figure 15 Math averages Figure 15 Min. 4.91450 3.66463 2.91470 2.41475 - - - 2.5 - - -0.3 300 2 2 0.4 -150 1.05 -200 45 0 -1000 45 9.99900 9.99900 9.87400 9.87400 - - - 2.5 - - -0.3 Max. 5.11063 3.85422 3.10038 2.59782 100 85 100 8 20 1.15 - 550 7 7 2.3 150 1.45 200 53 200 1000 55 10.0010 10.0010 10.1260 10.1763 250 125 100 8 20 1.15 - Unit ns ns ns ns ps ps ppm V/ns % V V mV V/ns V/ns V mV V mV % ps ps % ns ns ns ns ps ps ppm V/ns % V V TPERIODSSAbs 200-MHz CPUT and CPUC Absolute period, SSC TPERIODSSAbs 266-MHz CPUT and CPUC Absolute period, SSC TPERIODSSAbs 333-MHz CPUT and CPUC Absolute period, SSC TPERIODSSAbs 400-MHz CPUT and CPUC Absolute period, SSC TSKEW TCCJ LACC TR/TF TRFM V_max V_min VOX CPU0 to CPU1 CPUT/C Cycle to Cycle Jitter Long Term accuracy CPUT and CPUC Rise and Fall Times Rise/Fall Matching Max output Voltage Min output Voltage Crossing Point Voltage at 0.7V Swing
CPU at 3.3V (SSC refers to -0.5% spread spectrum) TR Output Rise Edge Rate Measured @ K8 test load using VOCM 400 mV, 0.850V to 1.650V TF VDIFF DIFF VCM VCM TDC TCYC TACCUM PCIEX TDC TPERIOD TPERIODSS TPERIODAbs Output Fall Edge Rate Differential Voltage Change in VDIFF_DC Magnitude Common Mode Voltage Change in VCM Duty Cycle Jitter, Cycle to Cycle Jitter, Accumulated PCIEXT and PCIEXC Duty Cycle Measured @ K8 test load using VOCM 400 mV, 1.650V to 0.850V Measured @ K8 test load (single-ended) Measured @ K8 test load (single-ended) Measured @ K8 test load (single-ended) Measured @ K8 test load (single-ended) Measured at VOX Measured at VOX Measured at VOX Measured at crossing point VOX
100-MHz PCIEXT and PCIEXC Period Measured at crossing point VOX @ 0.1s 100-MHz PCIEXT and PCIEXC Period, Measured at crossing point VOX @ 0.1s SSC 100-MHz PCIEXT and PCIEXC Absolute Period Measured at crossing point VOX @ 1 clock Measured at crossing point VOX @ 1 clock Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured differentially from 150 mV Measured single-endedly from 75 mV Math averages Figure 15 Math averages Figure 15
TPERIODSSAbs 100-MHz PCIEXT and PCIEXC Absolute Period, SSC TSKEW TCCJ LACC TR/TF TRFM V_max V_min Any PCIEXT/C to PCIEXT/C Clock Skew PCIEXT/C Cycle to Cycle Jitter PCIEXT/C Long Term Accuracy PCIEXT and PCIEXC Rise and Fall Times Rise/Fall Matching Max output Voltage Min output Voltage
Document #: 001-05677 Rev. *D
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CY28551-3
AC Electrical Specifications (continued)
Parameter VOX DOT TDC TPERIOD TPERIODAbs TCCJ LACC TLTJ TR/TF TRFM V_max V_min VOX TDC TPERIOD TPERIODSS TR/TF TCCJ TSKEW LACC LINK - 66 MHz TDC TPERIOD TPERIODSS TR/TF TCCJ TSKEW LACC PCI TDC TPERIOD TPERIODSS TPERIODAbs THIGH TLOW TR/TF LINK (66 MHz) Duty Cycle Measurement at 1.5V 45 14.9955 14.9955 1.0 - - - 45 29.99100 29.9910 29.49100 29.49100 12.0 12.0 1.0 55 15.0045 15.0045 4.0 250 175 300 55 30.00900 30.15980 30.50900 30.65980 - - 4.0 % ns ns V/ns ps ps ppm % ns ns ns ns ns ns V/ns Spread Disabled LINK (66 MHz) Period Measurement at 1.5V Spread Enabled LINK (66 MHz) Period, Measurement at 1.5V SSC LINK (66 MHz) rising and falling Edge Rate LINK (66 MHz) Cycle to Cycle Jitter Any LINK Clock Skew LINK (66 MHz) Long Term Accuracy PCI Duty Cycle Spread Disabled PCIF/PCI Period Spread Disabled PCIF/PCI Period PCIF and PCI high time PCIF and PCI low time PCIF and PCI rising and falling Edge Rate Measured between 0.8V and 2.0V Measurement at 1.5V Measurement at 1.5V Measured at crossing point VOX Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 2.4V Measurement at 0.4V Measured between 0.8V and 2.0V Description Crossing Point Voltage at 0.7V Swing DOT96T and DOT96C Duty Cycle DOT96T and DOT96C Period DOT96T/C Cycle to Cycle Jitter DOT96T/C Long Term Accuracy Long Term jitter SRCT and SRCC Rise and Fall Time Rise/Fall Matching Max output Voltage Min output Voltage Crossing Point Voltage at 0.7V Swing LINK (133 MHz) Duty Cycle Spread Enabled LINK (133 MHz) Period, SSC Measurement at 1.5V Measurement at 1.5V Measured at crossing point VOX Measured at crossing point VOX @ 0.1s Measured at crossing point VOX Measured at crossing point VOX Measurement taken from cross point VOX @ 10 s Measured differentially from 150 mV Measured single-endedly from 75 mV Math averages Figure 15 Math averages Figure 15 Condition Min. 300 45 10.4156 10.1656 - - - 2.5 - - -0.3 300 45 7.50 7.50 1.0 - - - Max. 550 55 10.4177 10.6677 250 300 700 8 20 1.15 - 550 55 7.56 7.56 4.0 250 175 300 Unit mV % ns ns ps ppm ps V/ns % V V mV % ns ns V/ns ps ps ppm
DOT96T and DOT96C Absolute Period Measured at crossing point VOX @ 0.1s
LINK - 133 MHz Spread Disabled LINK (133 MHz) Period Measurement at 1.5V
LINK (133 MHz) rising and falling Edge Measured between 0.8V and 2.0V Rate LINK (133 MHz) Cycle to Cycle Jitter Any LINK Clock Skew LINK (133 MHz) Long Term Accuracy Measurement at 1.5V Measurement at 1.5V Measured at crossing point VOX
Spread Enabled PCIF/PCI Period, SSC Measurement at 1.5V
TPERIODSSAbs Spread Enabled PCIF/PCI Period, SSC Measurement at 1.5V
Document #: 001-05677 Rev. *D
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CY28551-3
AC Electrical Specifications (continued)
Parameter TSKEW TCCJ USB TDC TPERIOD TPERIODAbs THIGH TLOW TR/TF TCCJ LACC TLTJ 24M TDC TPERIOD THIGH TLOW TR/TF TCCJ LACC TLTJ REF TDC TPERIOD TPERIODAbs TR/TF TCCJ TSKEW LACC TSTABLE Description Any PCI clock to Any PCI clock Skew PCIF and PCI Cycle to Cycle Jitter Duty Cycle Period Absolute Period USB high time USB low time Rising and Falling Edge Rate Cycle to Cycle Jitter 48M Long Term Accuracy Long Term jitter Condition Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V. In High Drive mode Measurement at 1.5V Measurement at 1.5V Measurement at 2.4V Measurement at 0.4V Measured between 0.8V and 2.0V Measurement at 1.5V Measured at crossing point VOX Measurement taken from cross point VOX@1 s Measurement at 1.5V. In High Drive mode Measurement at 1.5V Measurement at 2.4V Measurement at 0.4V Measured between 0.8V and 2.0V Measurement at 1.5V Measured at crossing point VOX Measurement taken from cross point VOX@1 s Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measured between 0.8V and 2.0V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Min. - - 45 20.83125 20.48125 8.094 7.694 1.0 - - - Max. 500 500 55 20.83542 21.18542 10.5 10.5 2.0 350 100 1.0 Unit ps ps % ns ns ns ns V/ns ps ppm ns
Duty Cycle Period USB high time USB low time Rising and Falling Edge Rate Cycle to Cycle Jitter 48M Long Term Accuracy Long Term jitter
45 41.6646 18.8323 18.8323 1.0 - - -
55 41.6688 18.8323 18.8323 4.0 350 100 1.0
% ns ns ns V/ns ps ppm ns
REF Duty Cycle REF Period REF Absolute Period REF Rise and Fall Times Edge rate REF Cycle to Cycle Jitter REF Clock to REF Clock Long Term Accuracy Clock Stabilization from Power-up
45 69.8203 68.82033 1.0 - - - -
55 69.8622 70.86224 4.0 1000 500 300 1.8
% ns ns V/ns ps ps ppm ms
ENABLE/DISABLE and SET-UP
Document #: 001-05677 Rev. *D
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CY28551-3
Test and Measurement Set-up
For PCI/USB and 24M Single-ended Signals and Reference The following diagrams show the test load configurations for the single-ended PCI, USB, 24M, and REF output signals. Figure 13. Single-ended Load Configuration
PCI/USB
22
50
Measurement Point
5 pF
12
50
Measurement Point
5 pF
REF
12
50
Measurement Point
5 pF
Figure 14. Single-ended Load Configuration HIGH DRIVE OPTION
12
50
Measurement Point
5 pF
PCI/USB
12
50
Measurement Point
5 pF
12
50
Measurement Point
5 pF
REF
12
50
12
Measurement Point
5 pF
50
Measurement Point
5 pF
Document #: 001-05677 Rev. *D
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CY28551-3
The following diagrams show the test load configuration for the differential CPU and PCIEX outputs.
Figure 15. Differential Load Configuration for 0.7 Push Pull Clock
L1 OUT+
22
L 1 = 0 .5 ", L 2 = 7 "
L2
50
50
M e a su re m e n t P o in t
2 pF
M e a su re m e n t P o in t
OUT-
L1
22
L2
2 pF
Figure 16. Differential Load Configuration for 3.3 Push Pull Clock
1 .2 5 V
CPUT_K8
L1
15 O hm
L2
T
PCB
3900 pF
L3
125 O hm M e a s u re m e n t P o in t
5 pF
169 O hm
1 .2 5 V
C PU C _K8
L1
15 O hm
L2
L3
TP C B
125 O hm M e a s u re m e n t P o in t
3900 pF
5 pF
Figure 17. Differential Measurement for Differential Output Signals (for AC Parameters Measurement)
Document #: 001-05677 Rev. *D
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CY28551-3
Figure 18. Single-ended Measurement for Differential Output Signals (for AC Parameters Measurement)
Figure 19. Single-ended Output Signals (for AC Parameters Measurement)
Ordering Information
Part Number Lead-free Package Type Product Flow
CY28551LFXC-3 CY28551LFXC-3T
56-pin QFN 56-pin QFN - Tape and Reel
Commercial, 0 to 85C Commercial, 0 to 85C
Document #: 001-05677 Rev. *D
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CY28551-3
Package Diagram
Figure 20. 56-Lead QFN 8 x 8 MM LF56A
TOP VIEW
SIDE VIEW
0.08[0.003] C
BOTTOM VIEW
A
7.90[0.311] 8.10[0.319] 7.70[0.303] 7.80[0.307] N 1
1.00[0.039] MAX. 0.05[0.002] MAX. 0.80[0.031] MAX. 0.20[0.008] REF. 0.18[0.007] 0.28[0.011] N PIN1 ID 0.20[0.008] R. 1 2 0.45[0.018]
0.80[0.031] DIA.
2
E-PAD
7.70[0.303] 7.80[0.307] 7.90[0.311] 8.10[0.319]
(PAD SIZE VARY BY DEVICE TYPE)
0.30[0.012] 0.50[0.020]
0-12 0.50[0.020] 6.45[0.254] 6.55[0.258]
0.24[0.009] 0.60[0.024]
(4X)
C SEATING PLANE
Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. Intel and Pentium are registered trademarks of Intel Corporation. SiS is a registered trademark of Silicon Integrated Systems. Dial-A-Frequency is a registered trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 001-05677 Rev. *D
Page 28 of 29
(c) Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
6.45[0.254] 6.55[0.258]
51-85144-*D
CY28551-3
Document History Page
Document Title: CY28551-3 Universal Clock Generator for Intel, VIA and SIS(R) Document Number: 001-05677 REV. ECN NO. Issue Date Orig. of Change Description of Change
** *A
409135 417501
See ECN See ECN
HGS HGS
New Data Sheet 1. Register alignment changed -BYTE 9 contains DF3_N8,DF2_N8,DF1_N8 -BYTE 10 contains DF1_N<7:0> -BYTE 11 contains DF2_N<7:0> -BYTE 12 contains DF3_N<7:0> 2. Add POWERGOOD status bit at BYTE6 [0] 3. Add CPU_STP#, PCI_STP# and CLKREQ# description Minor Change: To post on web 1. Change 48M/24_48M driving strength to high by default. 2. Change Revision ID (BYTE7[7:4]) to 0010. Minor Change: Corrected revision on spec footer & history page.
*B *C *D
460525 491623 492449
See ECN See ECN See ECN
RGL HGS FRA
Document #: 001-05677 Rev. *D
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